1. Field of the Invention
The present invention relates to a so-called SIP (System In Package) type semiconductor device in which two chips are mounted side by side on a die pad and sealed with resin.
2. Background Art
FIG. 9 is a plan view showing a conventional semiconductor device in which two chips are mounted side by side on a large die pad. Two chips 16 and 17 are mounted on a die pad 31. Here, the die pad 31 is larger than the chips 16 and 17. The chips 16 and 17 and a plurality of inner leads 15 are connected using a plurality of wires 20 and the chips 16 and 17 are interconnected. Slits 32 are formed in the die pad 31 between the chips 16 and 17. In the manufacturing process of this semiconductor device, when mounting the chips 16 and 17 on the die pad 31, the chips are aligned using the edge of the die pad 31 and the slits 32 as marks. Japanese Patent Laid-Open No. 2007-35853 describes a semiconductor device in which one chip is mounted on a die pad with marks placed thereon.
In recent years, there is proposed a semiconductor device whose die pad is made smaller than a chip to improve a temperature cycle characteristic. This is also being applied to an SIP type semiconductor device with two semiconductor chips mounted side by side on a die pad (e.g., see Japanese Patent Laid-Open No. 2003-110082).